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1 ltc1594l/ltc1598l applicatio s u descriptio u features typical applicatio n u the ltc ? 1594l/ltc1598l are 3v micropower, 12-bit sampling a/d converters that feature 4- and 8-channel multiplexers, respectively. they typically draw only 160 m a of supply current when converting and automatically power down to a typical supply current of 1na between conversions. the ltc1594l is available in a 16-pin so package and the ltc1598l is packaged in a 24-pin ssop. both operate on a 3v supply. the 12-bit, switched- capacitor, successive approximation adcs include a sample-and-hold. on-chip serial ports allow efficient data transfer to a wide range of microprocessors and microcontrollers over three or four wires. this, coupled with micropower consump- tion, makes remote location possible and facilitates trans- mitting data through isolation barriers. the circuit can be used in ratiometric applications or with an external reference. the high impedance analog inputs and the ability to operate with reduced spans (to 1.5v full scale) allow direct connection to sensors and transducers in many applications, eliminating the need for gain stages. 4- and 8-channel, 3v micropower sampling 12-bit serial i/o a/d converters n 12-bit resolution on 3v supply n low supply current: 160 m a typ n auto shutdown to 1na n guaranteed 3/4lsb max dnl n guaranteed 2.7v operation (5v versions available: ltc1594/ltc1598) n multiplexer: 4-channel mux (ltc1594l) 8-channel mux (ltc1598l) n separate mux output and adc input pins n mux and adc may be controlled separately n sampling rate: 10.5ksps n i/o compatible with qspi, spi and microwire tm , etc. n small package: 16-pin narrow so (ltc1594l) 24-pin ssop (ltc1598l) n pen screen digitizing n battery-operated systems n remote data acquisition n isolated data acquisition n battery monitoring n temperature measurement microwire is a trademark of national semiconductor corporation. , ltc and lt are registered trademarks of linear technology corporation. sample frequency (khz) 0.1 1 supply current ( m a) 10 100 1000 1 10 100 1594l/98l ta02 t a = 25 c v cc = 2.7v v ref = 2.5v f clk = 200khz supply current vs sample rate 12 m w, 8-channel, 12-bit adc samples at 200hz and runs off a 3v supply analog inputs 0v to 3v range 1k 1 f optional adc filter 20 21 22 23 24 1 2 3 8 4, 9 mpu serial data link microwire and spi compatable 10 6 5, 14 7 11 12 13 18 17 16 15, 19 1 f 3v 1594l/98l ta01 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com gnd csadc csmux clk d in d out nc nc adcin ltc1598l muxout v ref v cc + 12-bit sampling adc 8-channel mux
2 ltc1594l/ltc1598l (notes 1, 2) supply voltage (v cc ) to gnd ................................... 12v voltage analog reference .................... C 0.3v to (v cc + 0.3v) analog inputs .......................... C 0.3v to (v cc + 0.3v) digital inputs .........................................C 0.3v to 12v digital output .......................... C 0.3v to (v cc + 0.3v) absolute m axi m u m ratings w ww u power dissipation .............................................. 500mw operating temperature range LTC1594LCS/ltc1598lcg ..................... 0 c to 70 c ltc1594lis/ltc1598lig ................. C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c package/order i n for m atio n w u u consult factory for military grade parts. order part number order part number t jmax = 150 c, q ja = 110 c/ w 1 2 3 4 5 6 7 8 9 10 11 12 top view g package 24-lead plastic ssop 24 23 22 21 20 19 18 17 16 15 14 13 ch5 ch6 ch7 gnd clk csmux d in com gnd csadc d out nc ch4 ch3 ch2 ch1 ch0 v cc muxout adcin v ref v cc clk nc t jmax = 125 c, q ja = 120 c/ w top view s package 16-lead plastic so 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ch0 ch1 ch2 ch3 adcin v ref com gnd v cc muxout d in csmux clk v cc d out csadc reco m e n ded operati n g co n ditio n s u u u u w w symbol parameter conditions min typ max units v cc supply voltage (note 3) 2.7 3.6 v f clk clock frequency v cc = 2.7v (note 4) 200 khz t cyc total cycle time f clk = 200khz 95 m s t hdi hold time, d in after clk - v cc = 2.7v 450 ns t sucs setup time cs before first clk - (see operating sequence) v cc = 2.7v 2 m s t sudi setup time, d in stable before clk - v cc = 2.7v 600 ns t whclk clk high time v cc = 2.7v 1.5 m s t wlclk clk low time v cc = 2.7v 1.5 m s t whcs cs high time between data transfer cycles f clk = 200khz 25 m s t wlcs cs low time during data transfer f clk = 200khz 70 m s LTC1594LCS ltc1594lis ltc1598lcg ltc1598lig the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5)
3 ltc1594l/ltc1598l co n verter a n d m ultiplexer characteristics u w u parameter conditions min typ max min typ max units resolution (no missing codes) l 12 12 bits integral linearity error (note 6) l 3 3 lsb differential linearity error l 3/4 1 lsb offset error l 3 3 lsb gain error l 8 8 lsb ref input range (notes 7, 8) 1.5v to v cc + 0.05v v analog input range (notes 7, 8) C 0.05v to v cc + 0.05v v mux channel input leakage current off channel l 200 200 na muxout leakage current off channel l 200 200 na adcin input leakage current (note 9) l 1 1 m a symbol parameter conditions min typ max units s/(n + d) signal-to-noise plus distortion ratio 1khz input signal 68 db thd total harmonic distortion (up to 5th harmonic) 1khz input signal C 78 db sfdr spurious-free dynamic range 1khz input signal 80 db peak harmonic or spurious noise 1khz input signal C 80 db dy n a m ic accuracy u w digital a n d dc electrical characteristics u symbol parameter conditions min typ max units v ih high level input voltage v cc = 3.6v l 2.0 v v il low level input voltage v cc = 2.7v l 0.8 v i ih high level input current v in = v cc l 2.5 m a i il low level input current v in = 0v l C 2.5 m a v oh high level output voltage v cc = 2.7v, i o = 10 m a l 2.4 2.64 v v cc = 2.7v, i o = 360 m a l 2.1 2.30 v v ol low level output voltage v cc = 2.7v, i o = 400 m a l 0.4 v i oz hi-z output leakage cs = high l 3 m a i source output source current v out = 0v C 10 ma i sink output sink current v out = v cc 15 ma r ref reference input resistance cs = v ih 2700 m w cs = v il 60 k w i ref reference current cs = v cc l 0.001 2.5 m a t cyc 3 760 m s, f clk 25khz 50 m a t cyc 3 60 m s, f clk 200khz l 50 70 m a i cc supply current cs = v cc , clk = v cc , d in = v cc l 0.001 3 m a t cyc 3 760 m s, f clk 25khz 160 m a t cyc 3 60 m s, f clk 200khz l 160 320 m a LTC1594LCS/ltc1598lcg ltc1594lis/ltc1598lig the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) t a = 25 c, f smpl = 10.5khz. (note 5)
4 ltc1594l/ltc1598l symbol parameter conditions min typ max units t smpl analog input sample time see figure 1 in applications information 1.5 clk cycles f smpl(max) maximum sampling frequency see figure 1 in applications information l 10.5 khz t conv conversion time see figure 1 in applications information 12 clk cycles t ddo delay time, clk to d out data valid see test circuits l 600 1500 ns t dis delay time, cs - to d out hi-z see test circuits l 220 600 ns t en delay time, clk to d out enabled see test circuits l 180 500 ns t hdo time output data remains valid after clk c load = 100pf 520 ns t f d out fall time see test circuits l 60 180 ns t r d out rise time see test circuits l 80 180 ns t on enable turn-on time see figure 1 in applications information l 540 1200 ns t off enable turn-off time see figure 2 in applications information l 190 500 ns t open break-before-make interval l 125 350 ns c in input capacitance analog inputs on-channel 20 pf off-channel 5 pf digital input 5 pf ac characteristics note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to gnd. note 3: these devices are specified at 3v. consult factory for 5v specified devices (ltc1594/ltc1598). note 4: increased leakage currents at elevated temperatures cause the s/h to droop, therefore it is recommended that f clk 3 200khz at 85 c, f clk 3 75khz at 70 c and f clk 3 1khz at 25 c. note 5: v cc = 2.7v, v ref = 2.5v and clk = 200khz unless otherwise specified. csadc and csmux pins are tied together during the test. note 6: linearity error is specified between the actual end points of the a/d transfer curve. note 7: two on-chip diodes are tied to each reference and analog input which will conduct for reference or analog input voltages one diode drop below gnd or one diode drop above v cc . this spec allows 50mv forward bias of either diode for 2.7v v cc 3.6v. this means that as long as the reference or analog input does not exceed the supply voltage by more than 50mv, the output code will be correct. to achieve an absolute 0v to 3v input voltage range, it will therefore require a minimum supply voltage of 2.950v over initial tolerance, temperature variations and loading. note 8: recommended operating condition. note 9: channel leakage current is measured after the channel selection. typical perfor m a n ce characteristics u w supply current vs sample rate reference current vs temperature supply current vs temperature sample frequency (khz) 0.1 1 supply current ( m a) 10 100 1000 1 10 100 1594l/98l g01 t a = 25 c v cc = 2.7v v ref = 2.5v f clk = 200khz temperature ( c) ?5 60 supply current ( a) 100 180 220 260 ?5 25 45 125 1594l/98l g02 140 ?5 5 65 85 105 t a = 25 c v cc = 2.7v v ref = 2.5v f clk = 200khz f smpl = 10.5khz temperature ( c) ?5 43 reference current ( m a) 44 46 47 48 53 50 ?5 25 45 125 1594l/98l g03 45 51 52 49 ?5 5 65 85 105 v cc = 2.7v v ref = 2.5v f clk = 200khz f smpl = 10.5khz the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c.(note 5)
5 ltc1594l/ltc1598l typical perfor m a n ce characteristics u w change in linearity vs reference voltage change in gain vs reference voltage change in offset vs reference voltage reference voltage (v) 0.5 0 change in offset (lsb = 1/4096 v ref ) 0.5 1.0 1.5 2.0 2.5 3.0 1.0 1.5 2.0 2.5 1594l/98l g04 3.0 t a = 25 c v cc = 2.7v f clk = 200khz f smpl = 10.5khz reference voltage (v) 1.0 0 change in linearity (lsb) 0.05 0.15 0.20 0.25 0.50 0.35 1.4 1.8 2.0 2.8 1594l/98l g06 0.10 0.40 0.45 0.30 1.2 1.6 2.2 2.4 2.6 t a = 25 c v cc = 2.7v f clk = 200khz f smpl = 10.5khz reference voltage (v) 1.0 0 change in gain (lsb) ? ? ? ? ?0 ? 1.4 1.8 2.0 2.8 1594l/98l g07 ? ? ? ? 1.2 1.6 2.2 2.4 2.6 t a = 25 c v cc = 2.7v f clk = 200khz f smpl = 10.5khz input frequency (khz) 1 0 effective number of bits (enobs) s/(n + d) (db) 3 5 7 10 10 100 1594l/98l g09 1 4 6 9 12 11 8 62 56 74 68 50 2 t a = 25 c v cc = 2.7v f clk = 200khz f smpl = 10.5khz effective bits and s/(n + d) vs input frequency differential nonlinearity vs code code 0 ? differential nonlinearity error (lsb) 0.5 0 0.5 1 512 1024 1536 2048 1594l/98l g08 2560 3072 3584 4096 t a = 25 c v cc = 2.7v v ref = 2.5v f clk = 200khz spurious free dynamic range vs input frequency input frequency (khz) 1 0 spurious-free dynamic range (db) 20 40 60 80 10 100 1594l/98l g10 100 10 30 50 70 90 t a = 25 c v cc = 2.7v v ref = 2.5v f smpl = f smpl(max) frequency response input frequency (hz) 80 attenuation (%) 60 40 50 20 0 90 70 30 10 1k 100k 1m 10m 1594l/98l g12 100 10k (mux + a dc ) t a = 25 c v cc = 2.7v v ref = 2.5v f smpl = f smpl(max) change in offset vs temperature temperature ( c) 0 change in offset (lsb) 0.15 30 1594l/98l g05 0 0.10 10 20 40 0.15 0.20 0.20 0.10 0.05 0.05 50 60 70 v cc = 2.7v v ref = 2.5v f clk = 200khz f smpl = f smpl(max) s/(n + d) vs input level input level (db) ?5 signal-to-noise plus distortion (db) 40 50 60 ? 1594l/98/ g11 30 20 0 ?5 ?5 ?5 ?0 0 ?0 ?0 ?0 10 80 70 t a = 25 c v cc = 2.7v v ref = 2.5v f in = 1khz f smpl = f smpl(max)
6 ltc1594l/ltc1598l typical perfor m a n ce characteristics u w power supply feedthrough vs ripple frequency frequency (khz) 0 120 magnitude (db) 100 ?0 ?0 ?0 1.0 2.0 3.0 4.0 1594l/98l g13 ?0 0 0.5 1.5 2.5 3.5 t a = 25 c v cc = 2.7v v ref = 2.5v f in = 3.05khz f clk = 120khz f smpl = 7.5khz 4096 point fft plot ripple frequency (hz) ?0 feedthrough (db) ?0 ?0 ?0 ?0 0 ?0 ?0 ?0 ?0 1k 100k 1m 10m 1594l/98l g15 100 10k t a = 25 c v cc = 2.7v (v ripple = 1mv) v ref = 2.5v f clk = 200khz intermodulation distortion frequency (khz) 0 120 magnitude (db) 100 ?0 ?0 ?0 1.0 2.0 3.0 4.0 1594l/98l g14 ?0 0 0.5 1.5 2.5 3.5 t a = 25 c v cc = 2.7v v ref = 2.5v f1 = 2.05khz f2 = 3.05khz f smpl = 7.5khz maximum clock frequency vs source resistance source resistance ( w ) 10 clock frequency (khz) 120 130 150 170 100 1000 1594l/98l g16 200 140 160 180 190 input +input v in r source t a = 25 c v cc = 2.7v v ref = 2.5v sample-and-hold acquisition time vs source resistance source resistance ( w ) 1 100 s & h acquisition time (ns) 1000 10000 100 1000 10 10000 1594l/98l g17 t a = 25 c v cc = 2.7v v ref = 2.5v input +input v in r source + input channel leakage current vs temperature minimum clock frequency for 0.1lsb error vs temperature temperature ( c) 0 clock frequency (khz) 80 100 120 40 1594l/98l g18 60 40 0 10 20 30 60 70 50 20 2 v cc = 2.7v v ref = 2.5v temperature ( c) ?5 leakage current (na) 10 100 1000 105 1594l/98l g19 1 0.1 0.01 ?5 25 65 35 125 5 45 85 v cc = 2.7v v ref = 2.5v on channel off channel
7 ltc1594l/ltc1598l pi n fu n ctio n s uuu ltc1594l ch0 (pin 1): analog multiplexer input. ch1 (pin 2): analog multiplexer input. ch2 (pin 3): analog multiplexer input. ch3 (pin 4): analog multiplexer input. adcin (pin 5): adc input. this input is the positive analog input to the adc. connect this pin to muxout for normal operation. v ref (pin 6): reference input. the reference input defines the span of the adc. com (pin 7): negative analog input. this input is the negative analog input to the adc and must be free of noise with respect to gnd. gnd (pin 8): analog ground. gnd should be tied directly to an analog ground plane. csadc (pin 9): adc chip select input. a logic high on this input powers down the adc and three-states d out . a logic low on this input enables the adc to sample the selected channel and start the conversion. for normal operation, drive this pin in parallel with csmux. ltc1598l ch5 (pin 1): analog multiplexer input. ch6 (pin 2): analog multiplexer input. ch7 (pin 3): analog multiplexer input. gnd (pin 4): analog ground. gnd should be tied directly to an analog ground plane. clk (pin 5): shift clock. this clock synchronizes the serial data transfer to both mux and adc. it also determines the conversion speed of the adc. csmux (pin 6): mux chip select input. a logic high on this input allows the mux to receive a channel address. a logic low enables the selected mux channel and connects it to the muxout pin for a/d conversion. for normal operation, drive this pin in parallel with csadc. d in (pin 7): digital data input. the multiplexer address is shifted into this input. d out (pin 10): digital data output. the a/d conversion result is shifted out of this output. v cc (pin 11): power supply voltage. this pin provides power to the adc. it must be bypassed directly to the analog ground plane. clk (pin 12): shift clock. this clock synchronizes the serial data transfer to both mux and adc. csmux (pin 13): mux chip select input. a logic high on this input allows the mux to receive a channel address. a logic low enables the selected mux channel and connects it to the muxout pin for a/d conversion. for normal operation, drive this pin in parallel with csadc. d in (pin 14): digital data input. the multiplexer address is shifted into this input. muxout (pin 15): mux output. this pin is the output of the multiplexer. tie to adcin for normal operation. v cc (pin 16): power supply voltage. this pin should be tied to pin 11. com (pin 8): negative analog input. this input is the negative analog input to the adc and must be free of noise with respect to gnd. gnd (pin 9): analog ground. gnd should be tied directly to an analog ground plane. csadc (pin 10): adc chip select input. a logic high on this input deselects and powers down the adc and three- states d out . a logic low on this input enables the adc to sample the selected channel and start the conversion. for normal operation drive this pin in parallel with csmux. d out (pin 11): digital data output. the a/d conversion result is shifted out of this output. nc (pin 12): no connection. nc (pin 13): no connection. clk (pin 14): shift clock. this input should be tied to pin 5.
8 ltc1594l/ltc1598l pi n fu n ctio n s uuu v cc (pin 15): power supply voltage. this pin provides power to the a/d converter. it must be bypassed directly to the analog ground plane. v ref (pin 16): reference input. the reference input defines the span of the adc. adcin (pin 17): adc input. this input is the positive analog input to the adc. connect this pin to muxout for normal operation. muxout (pin 18): mux output. this pin is the output of the multiplexer. tie to adcin for normal operation. v cc (pin 19): power supply voltage. this pin should be tied to pin 15. ch0 (pin 20): analog multiplexer input. ch1 (pin 21): analog multiplexer input. ch2 (pin 22): analog multiplexer input. ch3 (pin 23): analog multiplexer input. ch4 (pin 24): analog multiplexer input. test circuits voltage waveforms for d out rise and fall times, t r , t f load circuit for t ddo , t r and t f d out 1.4v 3k 100pf test point 1594l/98l tc01 block diagra s w ltc1594l ch0 ch1 ch2 ch3 1 2 3 4 7 com gnd 8 1594l bd 9 13 12 14 10 csadc csmux clk d in d out adcin muxout 15 5 6 16 v ref v cc ltc1594l + 4-channel mux 12-bit sampling adc ltc1598l 1598l bd ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 + 8 com gnd 4, 9 10 6 5, 14 7 11 csadc csmux clk d in d out 12 13 nc nc adcin muxout 18 17 16 15, 19 v ref v cc ltc1598l 20 21 22 23 24 1 2 3 8-channel mux 12-bit sampling adc d out v ol v oh t r t f 1594l/98l tc02
9 ltc1594l/ltc1598l test circuits voltage waveforms for t en voltage waveforms for d out delay times, t ddo clk d out v il t ddo v ol v oh 1594l/98l tc03 d out waveform 1 (see note 1) v ih t dis 90% 10% d out waveform 2 (see note 2) csadc = csmux = cs note 1: waveform 1 is for an output with internal conditions such that the output is high unless disabled by the output control. note 2: waveform 2 is for an output with internal conditions such that the output is low unless disabled by the output control. 1594l/98l tc05 load circuit for t dis and t en d out 3k 100pf test point v cc t dis waveform 2, t en t dis waveform 1 1594l/98l tc04 voltage waveforms for t dis 1594l/98l tc06 csadc ltc1594l/ltc1598l 1 clk d out t en b11 v ol 2
10 ltc1594l/ltc1598l applicatio n s i n for m atio n wu u u overview the ltc1594l/ltc1598l are 3v micropower, 12-bit sampling a/d converters that feature 4- and 8-channel multiplexers respectively. they typically draw only 160 m a of supply current when sampling at 10.5khz. supply current drops linearly as the sample rate is reduced (see supply current vs sample rate). the adcs automatically power down when not performing conversions, drawing only leakage current. the ltc1594l is available in a 16-pin narrow so package and the ltc1598l is pack- aged in a 24-pin ssop. both devices operate on a single supply from 2.7v to 3.6v. the ltc1594l/ltc1598l contain a 12-bit, switched- capacitor adc, sample-and-hold, serial port and an external reference input pin. in addition, the ltc1594l has a 4-channel multiplexer and the ltc1598l provides an 8-channel multiplexer (see block diagram). they can measure signals floating on a dc common mode voltage and can operate with reduced spans to 1.5v. reducing the spans allow them to achieve 366 m v resolution. the ltc1594l/ltc1598l provide separate mux output and adc input pins to form an ideal muxout/adcin loop which economizes signal conditioning. the mux and adc of the devices can also be controlled individually through separate chip selects to enhance flexibility. serial interface for this discussion, we will assume that csmux and csadc are tied together and will refer to them as simply cs, unless otherwise specified. the ltc1594l/ltc1598l communicate with the micro- processor and other external circuitry via a synchronous, half duplex, 4-wire interface (see operating sequences in figures 1 and 2). clk en d1 d2 csmux = csadc = cs t cyc b5 b6 b7 b8 b9 b10 b11 hi-z d out ch0 to ch7 d in t conv hi-z t sucs null bit d0 b4 b3 b2 b1 b0* t smpl t on don? care adcin = muxout com = gnd *after completing the data transfer, if further clocks are applied with cs low, the adc will output lsb-first data then followed with zeros indefinitely 1594f/98f f01 figure 1. ltc1594l/ltc1598l operating sequence example: ch2, gnd
11 ltc1594l/ltc1598l applicatio n s i n for m atio n wu u u figure 2. ltc1594l/ltc1598l operating sequence example: all channels off clk en d1 d2 t cyc hi-z d out ch0 to ch7 d in t conv hi-z t sucs null bit d0 t off d0n? care adcin = muxout com = gnd 1594l/98l f02 dummy conversion csmux = csadc = cs break-before-make interval, t open . after a delay of t on (t off + t open ), the selected channel is switched on, allowing the adc in the chip to acquire input signal and start the conversion (see figures 1 and 2). after 1 null bit, the result of the conversion is output on the d out line. the selected channel remains on, until the next falling edge of cs. at the end of the data exchange, cs should be brought high. this resets the ltc1594l/ltc1598l and initiates the next data exchange. d in1 d in2 d out1 d out2 cs shift mux address in t smpl + 1 null bit shift a/d conversion result out 1594l/98l ai01 break-before-make the ltc1594l/ltc1598l provide a break-before-make interval from switching off all the channels simulta- neously to switching on the next selected channel once cs is pulled low. in other words, once cs is pulled low, data transfer the clk synchronizes the data transfer with each bit being transmitted on the falling clk edge and captured on the rising clk edge in both transmitting and receiving systems. the ltc1594l/ltc1598l first receive input data and then transmit back the a/d conversion results (half duplex). because of the half duplex operation, d in and d out may be tied together allowing transmission over just 3 wires: cs, clk and data (d in /d out ). data transfer is initiated by a rising chip select (cs) signal. after cs rises, the input data on the d in pin is latched into a 4-bit register on the rising edge of the clock. more than four input bits can be sent to the d in pin without problems, but only the last four bits clocked in before cs falls will be stored into the 4-bit register. this 4-bit input data word will select the channel in the muliplexer (see input data word and tables 1 and 2). to ensure correct operation, the cs must be pulled low before the next rising edge of the clock. once the cs is pulled low, all channels are simulta- neously switched off after a delay of t off to ensure a
12 ltc1594l/ltc1598l after a delay of t off , all the channels are switched off to ensure a break-before-make interval. after this interval, the selected channel is switched on allowing signal transmission. the selected channel remains on until the next falling edge of cs and the process repeats itself with the en bit being logic high. if the en bit is logic low, all the channels are switched off simultaneously after a delay of t off from cs being pulled low and all the channels remain off until the next falling edge of cs. input data word when cs is high, the ltc1594l/ltc1598l clock data into the d in inputs on the rising edge of the clock and store the data into a 4-bit register. the input data words are defined as follows: d0 en d2 d1 channel selection 1594l/98l ai02 en bit the first bit in the 4-bit register is an en bit. if the en bit is a logic high, as illustrated in figure 1, it enables the selected channel after a delay of t on when the cs is pulled low. if the en bit is logic low, as illustrated in figure 2, it disables all channels after a delay of t off when the cs is pulled low. multiplexer (mux) address the 3 bits of input word following the en bit select the channel in the mux for the requested conversion. for a given channel selection, the converter will measure the voltage of the selected channel with respect to the voltage on the com pin. tables 1 and 2 show the various bit combinations for the ltc1594l/ltc1598l channel selection. table 1. logic table for the ltc1594l channel selection channel status en d2 d1 do all off 0 x x x ch0 1 0 0 0 ch1 1 0 0 1 ch2 1 0 1 0 ch3 1 0 1 1 applicatio n s i n for m atio n wu u u table 2. logic table for the ltc1598l channel selection channel status en d2 d1 do all off 0 x x x ch0 1 0 0 0 ch1 1 0 0 1 ch2 1 0 1 0 ch3 1 0 1 1 ch4 1 1 0 0 ch5 1 1 0 1 ch6 1 1 1 0 ch7 1 1 1 1 transfer curve the ltc1594l/ltc1598l are permanently configured for unipolar only. the input span and code assignment for this conversion type is illustrated below. transfer curve 0v 1lsb v ref ?lsb v ref 4096 v ref ?lsb v ref v in 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1594l/98l ?ai03 1lsb = output code output code 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 input voltage v ref ?1lsb v ref ?2lsb 1lsb 0v input voltage (v ref = 2.500v) 2.49939v 2.49878v 0.00061v 0v 1594l/98l ?ai04
13 ltc1594l/ltc1598l applicatio n s i n for m atio n wu u u operation with d in and d out tied together the ltc1594l/ltc1598l can be operated with d in and d out tied together. this eliminates one of the lines required to communicate to the microprocessor (mpu). data is transmitted in both directions on a single wire. the processor pin connected to this data line should be configurable as either an input or an output. the ltc1594l/ltc1598l will take control of the data line after cs falling and before the 6th falling clk while the processor takes control of the data line when cs is high (see figure 3). therefore the processor port line must be switched to an input with cs being low to avoid a conflict. separate chip selects for mux and adc the ltc1594l/ltc1598l provide separate chip selects, csmux and csadc, to control mux and adc separately. this feature not only provides the flexibility to select a particular channel once for multiple conversions (see figure 4) but also maximizes the sample rate up to 20ksps (see figure 5). figure 4. selecting a channel once for multiple conversions clk en d1 d2 csadc csmux b5 b6 b7 b8 b9 b10 b11 hi-z d out ch0 to ch7 d in t conv hi-z t sucs null bit d0 b4 b3 b2 b1 b0 t smpl t on b5 b6 b7 b8 b9 b10 b11 hi-z t conv t sucs null bit d0 b4 b3 b2 b1 b0 t smpl adcin = muxout com = gnd 1594l/98l f04 don? care don? care 1 2 3 456 cs clk data (d in /d out ) en d2 d1 d0 b11 b10 ltc1594l/ltc1598l controls data line and sends a/d result back to mpu mpu controls data line and sends mux address to ltc1594l/ltc1598l processor must release data line after cs falling and before the 6th falling clk ltc1594l/ltc1598l takes control of data line after cs falling and before the 6th falling clk 1594l/98l f03 t sucs figure 3. ltc1594l/ltc1598l operation with d in and d out tied together
14 ltc1594l/ltc1598l applicatio n s i n for m atio n wu u u clk en d1 d2 csmux csadc b5 b6 b7 b8 b9 b10 b11 d out ch0 to ch7 d in t conv t sucs null bit d0 b4 b3 b2 b1 b0 en d1 t smpl t on t on b5 b6 b7 b8 b9 b10 b11 t conv t sucs null bit d0 d2 en d1 d0 d2 b4 b3 b2 b1 b0 t smpl adcin = muxout com = gnd 1594l/98l f05 b4 b3 b2 b1 b0 don? care don? care muxout/adcin loop economizes signal conditioning the muxout and adcin pins of the ltc1594l/ltc1598l form a very flexible external loop that allows program- mable gain amplifier (pga) and/or processing analog input signals prior to conversion. this loop is also a cost effective way to perform the conditioning, because only one circuit is needed instead of one for each channel. in the typical applications section, there are a few examples illustrating how to use the muxout/adcin loop to form a pga and to antialias filter several analog inputs. achieving micropower performance with typical operating currents of 160 m a and automatic shutdown between conversions, the ltc1594l/ ltc1598l achieve extremely low power consumption over a wide range of sample rates (see figure 6). the auto shutdown allows the supply current to drop with reduced sample rate. several things must be taken into account to achieve such a low power consumption. shutdown the ltc1594l/ltc1598l are equipped with automatic shutdown features. they draw power when the cs pin is low. the bias circuits and comparator of the adc powers down and the reference input becomes high impedance at the end of each conversion leaving the clk running to clock out the lsb first data or zeroes (see figures 1 and 2). when the cs pin is high, the adc powers down completely leaving the clk running to clock the input data word into mux. if the cs, d in and clk are not running rail-to-rail, the input logic buffers will draw currents. these currents may be large compared to the typical supply current. to obtain the lowest supply current, run the cs, d in and clk pins rail-to-rail. d out loading capacitive loading on the digital output can increase power consumption. a 100pf capacitor on the d out pin can add more than 50 m a to the supply current at a 200khz clock frequency. an extra 50 m a or so of current goes into charging and discharging the load capacitor. the same goes for digital lines driven at a high frequency by any logic. the (c)(v)(f) currents must be evaluated and the troublesome ones minimized. figure 5. use separate chip selects to maximize sample rate figure 6. automatic power shutdown between conversions allows power consumption to drop with sample rate sample frequency (khz) 0.1 1 supply current ( m a) 10 100 1000 1 10 100 1594l/98l g01 t a = 25 c v cc = 2.7v v ref = 2.5v f clk = 200khz
15 ltc1594l/ltc1598l applicatio n s i n for m atio n wu u u board layout considerations grounding and bypassing the ltc1594l/ltc1598l are easy to use if some care is taken. they should be used with an analog ground plane and single point grounding techniques. the gnd pin should be tied directly to the ground plane. the v cc pin should be bypassed to the ground plane with a 10 m f tantalum capacitor with leads as short as possible. if the power supply is clean, the ltc1594l/ltc1598l can also operate with smaller 1 m f or less surface mount or ceramic bypass capacitors. all analog inputs should be referenced directly to the single point ground. digital inputs and outputs should be shielded from and/or routed away from the reference and analog circuitry. sample-and-hold both the ltc1594l/ltc1598l provide a built-in sample- and-hold (s&h) function to acquire signals through the selected channel, assuming the adcin and muxout pins are tied together. the s & h of these parts acquire input signals through the selected channel relative to com input during the t smpl time (see figure 7). single-ended inputs the sample-and-hold of the ltc1594l/ltc1598l allows conversion of rapidly varying signals. the input voltage is sampled during the t smpl time as shown in figure 7. the sampling interval begins after t on time once the cs is pulled low and continues until the second falling clk edge after the cs is low (see figure 7). on this falling clk figure 7. ltc1594l/ltc1598l adcin and com input settling windows clk d in d out muxout = adcin ch0 to ch7 sample hold ?nalog?input must settle during this time t smpl t on t conv csadc = csmux = cs d2 d1 en d0 don? care 1st bit test ?om?input must settle during this time b11 com 1594l/98l f07
16 ltc1594l/ltc1598l applicatio n s i n for m atio n wu u u edge, the s & h goes into hold mode and the conversion begins. the voltage on the com input must remain constant and be free of noise and ripple throughout the conversion time. otherwise, the conversion operation may not be performed accurately. the conversion time is 12 clk cycles. therefore, a change in the com input voltage during this interval can cause conversion errors. for a sinusoidal voltage on the com input this error would be: v error(max) = v peak (2 p )(f)(com)12/f clk where f(com) is the frequency of the com input voltage, v peak is its peak amplitude and f clk is the frequency of the clk. in most cases, v error will not be significant. for a 60hz signal on the com input to generate a 0.5lsb error (305 m v) with the converter running at clk = 200khz, its peak value would have to be 5.266mv. analog inputs because of the capacitive redistribution a/d conversion techniques used, the analog inputs of the ltc1594l/ ltc1598l have capacitive switching input current spikes. these current spikes settle quickly and do not cause a problem. however, if large source resistances are used or if slow settling op amps drive the inputs, care must be taken to insure that the transients caused by the current spikes settle completely before the conversion begins. analog input settling the input capacitor of the ltc1594l/ltc1598l is switched onto the selected channel input during the t smpl time (see figure 7) and samples the input signal within that time. the sample phase is at least 1 1/2 clk cycles before conver- sion starts. the voltage on the analog input must settle completely within t smpl . minimizing r source + and c1 will improve the input settling time. if a large analog input source resistance must be used, the sample time can be increased by using a slower clk frequency. com input settling at the end of the t smpl , the input capacitor switches to the com input and conversion starts (see figures 1 and 7). during the conversion, the analog input voltage is effectively held by the sample-and-hold and will not affect the conversion result. however, it is critical that the com input voltage settles completely during the first clk cycle of the conversion time and be free of noise. minimizing r source C and c2 will improve settling time. if a large com input source resistance must be used, the time allowed for settling can be extended by using a slower clk frequency. input op amps when driving the analog inputs with an op amp it is important that the op amp settle within the allowed time (see figure 7). again, the analog and com input sampling times can be extended as described above to accommodate slower op amps. most op amps, including the lt ? 1006 and lt1413 single supply op amps, can be made to settle well even with the minimum settling windows of 7.5 m s (analog input) which occur at the maximum clock rate of 200khz. source resistance the analog inputs of the ltc1594l/ltc1598l look like a 20pf capacitor (c in ) in series with a 1k resistor (r on ) and a 90 w channel resistance as shown in figure 8. c in gets switched between the selected analog and com inputs once during each conversion cycle. large external source resistors and capacitances will slow the settling of the inputs. it is important that the overall rc time constants be short enough to allow the analog inputs to completely settle within the allowed time. figure 8. analog input equivalent circuit r on 1k r on 90 w c in 20pf ltc1594l ltc1598l ?nalog input r source + v in + c1 ?om input muxout mux adcin r source v in c2 1594l/98l f08
17 ltc1594l/ltc1598l input leakage current input leakage currents can also create errors if the source resistance gets too large. for instance, the maximum input leakage specification of 200na (at 85 c) flowing through a source resistance of 600 w will cause a voltage drop of 120 m v or 0.2lsb. this error will be much reduced at lower temperatures because leakage drops rapidly (see typical curve input channel leakage current vs temperature). reference inputs the reference input of the ltc1594l/ltc1598l is effec- tively a 50k resistor from the time cs goes low to the end of the conversion. the reference input becomes a high impedance node at any other time (see figure 9). since the voltage on the reference input defines the voltage span of the a/d converter, the reference input should be driven by a reference with low r out (ex. lt1004, lt1019 and lt1021) or a voltage source with low r out . reduced reference operation the effective resolution of the ltc1594l/ltc1598l can be increased by reducing the input span of the convert- ers. the ltc1594l/ltc1598l exhibit good linearity and gain over a wide range of reference voltages (see typical curves change in linearity vs reference voltage and change in gain vs reference voltage). however, care must be taken when operating at low values of v ref because of the reduced lsb step size and the resulting higher accuracy requirement placed on the converters. the following factors must be considered when operat- ing at low v ref values: 1. offset 2. noise 3. conversion speed (clk frequency) offset with reduced v ref the offset of the ltc1594l/ltc1598l has a larger effect on the output code when the adcs are operated with reduced reference voltage. the offset (which is typically a fixed voltage) becomes a larger fraction of an lsb as the size of the lsb is reduced. the typical curve of change in offset vs reference voltage shows how offset in lsbs is related to reference voltage for a typical value of v os . for example, a v os of 122 m v which is 0.2lsb with a 2.5v reference becomes 0.5lsb with a 1v reference and 2.5lsbs with a 0.2v reference. if this offset is unaccept- able, it can be corrected digitally by the receiving system or by offsetting the com input of the ltc1594l/ ltc1598l. noise with reduced v ref the total input referred noise of the ltc1594l/ltc1598l can be reduced to approximately 400 m v peak-to-peak using a ground plane, good bypassing, good layout techniques and minimizing noise on the reference inputs. this noise is insignificant with a 5v reference but will become a larger fraction of an lsb as the size of the lsb is reduced. for operation with a 2.5v reference, the 400 m v noise is only 0.66lsb peak-to-peak. in this case, the ltc1594l/ ltc1598l noise will contribute virtually no uncertainty to the output code. however, for reduced references the noise may become a significant fraction of an lsb and cause undesirable jitter in the output code. for example, with a 1.25v reference this same 400 m v noise is 1.32lsb peak-to-peak. this will reduce the range of input voltages over which a stable output code can be achieved by 1lsb. if the reference is further reduced to 1v, the 400 m v noise becomes equal to 1.65lsbs and a stable code may be difficult to achieve. in this case, averaging multiple readings may be necessary. this noise data was taken in a very clean setup. any setup induced noise (noise or ripple on v cc , v ref or v in ) will add to the internal noise. the lower the reference voltage to be used the more critical it becomes to have a clean, noise free setup. ltc1594l ltc1598l ref + r out v ref 1 4 gnd 1594l/98l f09 figure 9. reference input equivalent circuit applicatio n s i n for m atio n wu u u
18 ltc1594l/ltc1598l conversion speed with reduced v ref with reduced reference voltages, the lsb step size is reduced and the ltc1594l/ltc1598l internal compara- tor overdrive is reduced. therefore, it may be necessary to reduce the maximum clk frequency when low values of v ref are used. dynamic performance the ltc1594l/ltc1598l have exceptional sampling capability. fast fourier transform (fft) test techniques are used to characterize the adcs frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algorithm, the adcs spectral con- tent can be examined for frequencies outside the funda- mental. figure 10 shows a typical ltc1594l/ltc1598l plot. applicatio n s i n for m atio n wu u u effective number of bits the effective number of bits (enobs) is a measurement of the resolution of an adc and is directly related to s/(n + d) by the equation: enob = [s/(n + d) C 1.76]/6.02 where s/(n + d) is expressed in db. at the maximum sampling rate of 10.5khz with a 5v supply, the ltc1594l/ ltc1598l maintain above 10.7 enobs at 10khz input frequency. above 10khz the enobs gradually decline, as shown in figure 11, due to increasing second harmonic distortion. the noise floor remains low. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamen- tal itself. the out-of-band harmonics alias into the fre- quency band between dc and half of the sampling frequency. thd is defined as: thd = ++++ 20log vvv v v 2 2 3 2 4 2 n 2 1 ... where v 1 is the rms amplitude of the fundamental frequency and v 2 through v n are the amplitudes of the second through the n th harmonics. the typical thd signal-to-noise ratio the signal-to-noise plus distortion ratio (s/n + d) is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other fre- quency components at the adcs output. the output is band limited to frequencies above dc and below one half the sampling frequency. figure 11 shows a typical spec- tral content with a 10.5khz sampling rate. figure 10. ltc1594l/ltc1598l nonaveraged, 4096 point fft plot frequency (khz) 0 120 magnitude (db) 100 ?0 ?0 ?0 1.0 2.0 3.0 4.0 1594l/98l g13 ?0 0 0.5 1.5 2.5 3.5 t a = 25 c v cc = 2.7v v ref = 2.5v f in = 3.05khz f clk = 120khz f smpl = 7.5khz figure 11. effective bits and s/(n + d) vs input frequency input frequency (khz) 1 0 effective number of bits (enobs) s/(n + d) (db) 3 5 7 10 10 100 1594l/98l g09 1 4 6 9 12 11 8 62 56 74 68 50 2 t a = 25 c v cc = 2.7v f clk = 200khz f smpl = 10.5khz
19 ltc1594l/ltc1598l specification in the dynamic accuracy table includes the 2nd through 5th harmonics. with a 1khz input signal, the ltc1594l/ltc1598l have typical thd of 78db with v cc = 2.7v. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlin- earity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoi- dal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies f a and f b are applied to the adc input, nonlinearities in the adc transfer function can create distortion products at sum and differ- ence frequencies of mf a nf b , where m and n = 0, 1, 2, 3, etc. for example, the 2nd order imd terms include (f a + f b ) and (f a C f b ) while 3rd order imd terms include (2f a + f b ), (2f a C f b ), (f a + 2f b ), and (f a C 2f b ). if the two input sine waves are equal in magnitudes, the value (in db) of the 2nd order imd products can be expressed by the follow- ing formula: applicatio n s i n for m atio n wu u u typical applicatio n s n u microprocessor interfaces the ltc1594l/ltc1598l can interface directly (without external hardware) to most popular microprocessors (mpu) synchronous serial formats including microwire, spi and qspi. if an mpu without a dedi- cated serial port is used, then three of the mpus parallel port lines can be programmed to form the serial link to the ltc1594l/ltc1598l. included here is one serial interface example. motorola spi (mc68hc05) the mc68hc05 has been chosen as an example of an mpu with a dedicated serial port. this mpu transfers data msb- first and in 8-bit increments. the d in word sent to the data register starts the spi process. with three 8-bit transfers the a/d result is read into the mpu. the second 8-bit transfer clocks b11 through b7 of the a/d conversion result into the processor. the third 8-bit trans- fer clocks the remaining bits b6 through b0 into the mpu. anding the second byte with 1f hex clears the three most significant bits and anding the third byte with fe hex clears the least significant bit. shifting the data to the right by one bit results in a right justified word. imd f f mplitude f f ab ab () = () ? ? 20log a amplitude at f a peak harmonic or spurious noise the peak harmonic or spurious noise is the largest spectral component excluding the input signal and dc. this value is expressed in dbs relative to the rms value of a full-scale input signal. full-power and full-linear bandwidth the full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full-scale input. the full-linear bandwidth is the input frequency at which the effective bits rating of the adc falls to 11 bits. beyond this frequency, distortion of the sampled input signal increases. the ltc1594l/ltc1598l have been designed to optimize input bandwidth, allowing the adcs to undersample input signals with frequencies above the converters nyquist frequency.
20 ltc1594l/ltc1598l typical applicatio n s n u lda #$52 configuration data for serial peripheral control register (interrupts disabled, output enabled, master, norm = 0, ph = 0, clk/16) sta $0a load configuration data into location $0a (spcr) lda #$ff configuration data for i/o ports (all bits are set as outputs) sta $04 load configuration data into port a ddr ($04) sta $05 load configuration data into port b ddr ($05) sta $06 load configuration data into port c ddr ($06) lda #$08 put d in word for ltc1598l into accumulator (ch0 with respect to gnd) sta $50 load d in word into memory location $50 start bset 0,$02 bit 0 port c ($02) goes high (cs goes high) lda $50 load d in word at $50 into accumulator sta $0c load d in word into spi data register ($0c) and start clocking data loop1 tst $0b test status of spif bit in spi status register ($0b) mc68hc05 code bpl loop1 loop if not done with transfer to previous instruction bclr 0,$02 bit 0 port c ($02) goes low (cs goes low) lda $0c load contents of spi data register into accumulator sta $0c start next spi cycle loop2 tst $0b test status of spif bpl loop2 loop if not done lda $0c load contents of spi data register into accumulator sta $0c start next spi cycle and #$if clear 3 msbs of first d out word sta $00 load port a ($00) with msbs loop3 tst $0b test status of spif bpl loop3 loop if not done lda $0c load contents of spi data register into accumulator and #$fe clear lsb of second d out word sta $01 load port b ($01) with lsbs jmp start go back to start and repeat program 1594l/98l ta04 d out from ltc1598l stored in mc68hc05 ram b1 b0 0 b2 b3 b5 b6 b4 0 0 lsb msb #00 #01 0 b11 b10 b9 b8 b7 clk d in csmux csadc analog inputs c0 sck mc68hc05 d out mosi ltc1598l byte 1 byte 2 miso hardware and software interface to motorola mc68hc05 data exchange between ltc1598l and mc68hc05 csmux = csadc = cs clk d out mpu received word 1594l/98l ta03 b3 b7 b6 b5 b4 b2 b1 b0 b1 b2 b11 b10 b9 b8 d in mpu transmit word byte 3 byte 2 en d2 0d1 x d0 byte 1 x x x x x x x 000 x x x xx x x x byte 3 byte 2 byte 1 b10 ? ? 0 b11 b9 b7 b8 b6 b5 b3 b4 b2 b1 b1 b0 don? care d1 d2 ? ?? ? ? ??? do en
21 ltc1594l/ltc1598l typical applicatio n s n u multichannel a/d uses a single antialiasing filter this circuit demonstrates how the ltc1598ls indepen- dent analog multiplexer can simplify design of a 12-bit data acquisition system. all eight channels are muxed into a single 1khz, 4th order sallen-key antialiasing filter, which is designed for single supply operation. since the ltc1598ls data converter accepts inputs from ground to the positive supply, rail-to-rail op amps were chosen for the filter to maximize dynamic range. the lt1368 dual rail- to-rail op amp is designed to operate with 0.1 m f load capacitors (c1 and c2). these capacitors provide fre- quency compensation for the amplifiers and help reduce the amplifiers output impedance and improve supply rejection at high frequencies. the filter contributes less than 1lsb of error due to offsets and bias currents. the filters noise and distortion are less than C72db for a 100hz, 2v p-p offset sine input. the combined mux and a/d errors result in an integral nonlinearity error of 3lsb (maximum) and a differential nonlinearity error of 3/4lsb (maximum). the typical signal-to-noise plus distortion ratio is 68db, with approxi- mately C78db of total harmonic distortion. the ltc1598l is programmed through a 4-wire serial interface that is compatible with microwire, spi and qspi. maximum serial clock speed is 200khz, which corresponds to a 10.5khz sampling rate. the complete circuit consumes approximately 600 m a from a single 3v supply. simple data acquisition system takes advantage of the ltc1598ls muxout/adcin pins to filter analog signals prior to a/d conversion 1594l/98l ta05 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 20 21 22 23 24 1 2 3 + 8-channel mux 8 com gnd 4, 9 10 6 5, 14 7 11 csadc csmux clk d in d out 12 13 nc nc 12-bit sampling adc serial data link microwire and spi compatible adcin muxout 18 3 8 1 2 17 16 3.3v 3.3v 15, 19 c7 1 m f v ref v cc ltc1598l c6 0.1 m f + c2 0.015 m f c8 0.01 m f r2 7.5k r3 7.5k r4 7.5k r1 7.5k c4 0.03 m f c3 0.1 m f c5 0.015 m f c1 0.03 m f 1/2 lt1368 5 7 6 4 + 1/2 lt1368
22 ltc1594l/ltc1598l typical applicatio n s n u using muxout/adcin loop as pga this figure shows the ltc1598ls muxout/adcin pins and an lt1368 being used to create a single channel pga with eight noninverting gains. combined with the ltc1391, the system can expand to eight channels and eight gains for each channel. using the ltc1594l, the pga is reduced to four gains. the output of the lt1368 drives the adcin and the resistor ladder. the resistors above the selected mux channel form the feedback for the lt1368. the gain for this amplifier is r s1 /r s2 + 1. r s1 is the summation of the resistors above the selected mux channel and r s2 is using the muxout/adcin pins of the ltc1598l to form a pga. the ltc1391 mux allows eight input channels to be digitized the summation of the resistors below the selected mux channel. if ch0 is selected, the gain is 1 since r s1 is 0. table 1 shows the gain for each mux channel. the lt1368 dual rail-to-rail op amp is designed to operate with 0.1 m f load capacitors. these capacitors provide frequency com- pensation for the amplifiers, help reduce the amplifiers output impedance and improve supply rejection at high frequencies. because the lt1368s i b is low, the r on of the selected channel will not affect the gain given by the formula above. 1594l/98l ta06 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 20 21 22 23 24 1 2 3 64r 32r 16r 8r 4r 2r r r + 8 com 18 muxout = daisy chain configuration for the ltc1391 and the ltc1598l gnd 4, 9 10 6 5, 14 11 7 csadc csmux clk d out d in 12 13 nc nc 12-bit sampling adc 8-channel mux 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ltc1391 3v 1 m f adcin 17 16 15, 19 1 m f 0.1 m f 3v 1 m f 3v v ref v cc + ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 v + d v d out d in cs clk gnd 1/2 lt1368 ltc1598l m p/ m c 3(5) 2(6) 1(7) 4 8
23 ltc1594l/ltc1598l g package 24-lead plastic ssop (0.209) (ltc dwg # 05-08-1640) dimensions in inches (millimeters) unless otherwise noted. package descriptio n u s package 16-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. g24 ssop 1098 0.13 ?0.22 (0.005 ?0.009) 0 ?8 0.55 ?0.95 (0.022 ?0.037) 5.20 ?5.38** (0.205 ?0.212) 7.65 ?7.90 (0.301 ?0.311) 1234 5 6 7 8 9 10 11 12 8.07 ?8.33* (0.318 ?0.328) 21 22 18 17 16 15 14 13 19 20 23 24 1.73 ?1.99 (0.068 ?0.078) 0.05 ?0.21 (0.002 ?0.008) 0.65 (0.0256) bsc 0.25 ?0.38 (0.010 ?0.015) note: dimensions are in millimeters dimensions do not include mold flash. mold flash shall not exceed 0.152mm (0.006") per side dimensions do not include interlead flash. interlead flash shall not exceed 0.254mm (0.010") per side * ** 0.016 ?0.050 (0.406 ?1.270) 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) 1 2 3 4 5 6 7 8 0.150 ?0.157** (3.810 ?3.988) 16 15 14 13 0.386 ?0.394* (9.804 ?10.008) 0.228 ?0.244 (5.791 ?6.197) 12 11 10 9 s16 1098 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) typ 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) bsc dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * **
24 ltc1594l/ltc1598l ? linear technology corporation 1997 15948lfa lt/tp 0500 2k rev a ? printed in usa typical applicatio n u related parts part number description comments ltc1096/ltc1098 8-pin so, micropower 8-bit adcs low power, small size, low cost ltc1096l/ltc1098l 8-pin so, 2.65v micropower 8-bit adcs low power, small size, low cost ltc1196/ltc1198 8-pin so, 1msps 8-bit adcs low power, small size, low cost ltc1282 3v high speed parallel 12-bit adc 140ksps, complete with v ref , clk, sample-and-hold ltc1285/ltc1288 8-pin so, 3v, micropower adcs 1- or 2-channel, auto shutdown ltc1286/ltc1298 8-pin so, 5v, micropower adcs 1- or 2-channel, auto shutdown ltc1289 multiplexed 3v, 12-bit adc 8-channel 12-bit serial i/o ltc1296 multiplexed 5v, 12-bit adc 8-channel 12-bit serial i/o ltc1415 5v high speed parallel 12-bit adc 1.25msps, complete with v ref , clk, sample-and-hold ltc1594 4-channel, 5v micropower 12-bit adc low power, small size, low cost ltc1598 8-channel, 5v micropower 12-bit adc low power, small size, low cost using the ltc1598l and ltc1391 as an 8-channel differential 12-bit adc system 1594l/98l ta07 20 21 22 23 24 1 2 3 8 com gnd 4, 9 10 6 5, 14 7 11 csadc csmux clk d in d out 12 13 nc nc adcin muxout 18 17 16 15, 19 1 f 1 f 3v v ref v cc 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ltc1391 ch0 ch7 d in clk cs d out 3v ltc1598l = daisy chain configuration for the ltc1391 and the ltc1598l ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 + 12-bit sampling adc 8-channel mux ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 v + d v d out d in cs clk gnd linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com

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